AI sovereignty: Understanding India’s AI chip potential in the global GPU race

Yesterday, I discussed the three pillars of AI sovereignty. Today, I’m diving into the first pillar—hardware fabrication—and examining where India stands in the global AI chip and GPU landscape.

Manufacturing technology and process nodes

India’s semiconductor production today is anchored in legacy process nodes—from 65nm down to 28nm—with only incremental progress toward 14nm. For example, the Tata-Powerchip Semiconductor Manufacturing Corporation (PSMC) joint venture in Dholera, Gujarat, is set to produce 28nm chips by 2026. These chips, aimed at automotive, IoT, and power management applications, are produced at giant scale—48 million per day. The wafer factory being set up in parallel, however, has a more modest scale, targeting just 50,000 wafer starts per month (WSPM). When compared to global benchmarks (like TSMC), this capacity is minuscule.

Critically, India’s fabs rely on deep ultraviolet (DUV) lithography systems from ASML and Nikon. Without access to extreme ultraviolet (EUV) lithography—the technology essential for fabricating chips below 10nm—India remains confined to older, less efficient processes. This technological limitation directly affects the power efficiency and performance of chips, posing a significant barrier for advanced GPUs and AI workloads.

Indigenous efforts and design strength

With about 20% of the world’s IC design talent, India has launched several initiatives that highlight its design prowess. Consider the Shakti processor—a RISC-V initiative from IIT-Madras that spans a broad range from 180nm (for space applications) to 22nm FinFET designs for more advanced needs. Similarly, InCore Semiconductor is developing high-performance RISC-V cores tailored for AI/ML tasks, while Mindgrove Technologies is focused on secure IoT SoCs. Supported by government schemes like the Design-Linked Incentive (DLI) Program, these projects underscore India’s burgeoning design and IP capabilities.

However, the critical challenge remains: how do we translate this exceptional design talent into high-end manufacturing? Without bridging this gap, innovative ideas risk remaining trapped in simulation labs rather than powering real-world AI applications.

Production scale and infrastructure challenges

Despite its robust design ecosystem, India’s overall semiconductor output accounts for less than 2% of global electronics production. The planned capacity of the Tata-PSMC fab—targeting 50,000 WSPM—is a mere fraction of what global leaders achieve. For instance, TSMC’s state-of-the-art fabs can reach capacities of up to 1.5 million WSPM for 3nm nodes.

Furthermore, India’s manufacturing ecosystem is burdened by:

Material Dependencies: Essential inputs such as high-purity argon, photoresists, and silicon wafers are largely imported, leaving the supply chain vulnerable.

Infrastructure Gaps: Semiconductor fabs require uninterrupted power, ultra-pure water, and sophisticated logistics systems—resources that are inconsistent across many Indian regions.

Global benchmarks: How does India compare?

TSMC: As the global leader in semiconductor fabrication, TSMC manufactures chips at the cutting-edge 3nm node and is already planning for 2nm by 2025. Their production leverages roughly 20 EUV layers, delivering up to 18% higher performance and 32% lower power consumption compared to 5nm processes.

ASML: The sole supplier of EUV lithography, ASML’s TWINSCAN NXE:3600D systems—costing around US$200 million each—are indispensable for producing chips below 7nm. Without these systems, advanced node fabrication would simply be unattainable.

NVIDIA: A fabless design titan, NVIDIA’s GPUs—such as the Hopper (fabricated at 5nm) and the upcoming Blackwell (projected at 4nm)—deliver industry-leading efficiency, with performance metrics around 4.8 TFLOPS per watt for AI workloads. This success stems from a tightly integrated ecosystem that marries cutting-edge design with advanced manufacturing processes provided by partners like TSMC.

Huawei: Despite facing geopolitical constraints, Huawei’s HiSilicon division once produced competitive chips like the Kirin 9000S on a 7nm node using multipatterning techniques via SMIC. However, these methods involve multiple patterning steps, which increase defect density and production costs—clearly demonstrating the advantages of EUV-enabled processes.

India’s exceptional design talent and innovative projects are undeniable. Yet, its manufacturing ecosystem remains a critical bottleneck. Without access to advanced process nodes and EUV lithography, Indian fabs are locked into legacy technologies, making it extremely challenging to produce the state-of-the-art AI chips and GPUs that will drive the next wave of technological innovation.

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If you have any questions or thoughts, don't hesitate to reach out. You can find me as @viksit on Twitter.